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The Test Method is applicable to categories of wafers specified in SEMI M1 used in advanced IC manufacturing
Equipment suppliers benefit from the ability to develop and market a single SECS-II interface that satisfies most customers
SEMI E1 — Specification for 3
This Test Method is also applicable to off-line measurement provided that the requirements of the test method are satisfied
MF172700 - SEMI MF1727 - Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers StdPbc-0619 The Test Method is applicableNOTICE: This Document was reapproved with minor editorial changes. Defects induced by thermal processing of silicon wafers may adversely influence device performance and yield. These defects are influenced directly by contamination, ambient atmosphere, temperature, time at temperature, and rate of change of temperature to which the specimens are subjected. Conditions vary significantly among device manufacturing technologies. The thermal cycling